1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor element, and more particularly, to a method of manufacturing a semiconductor element, such as an IC (Integrated Circuit), a MOS (Metal Oxide Semiconductor), and an insulated gate bipolar transistor (hereinafter, abbreviated to IGBT).
2. Description of the Related Art
In recent years, integrated circuits (ICs) have been most commonly used in important sections in a computer or a communication device. In such ICs, a number of transistors and resistors are connected so as to form electric circuits that are integrated onto one chip. Of these ICs, those including power semiconductor elements are referred to as power ICs.
An IGBT is a power element provided with both the high speed switching and the voltage driving characteristics of a MOSFET and the low on-voltage characteristic of a bipolar transistor. The IGBT has been expanding from industrial applications, which include devices such as general-purpose inverters, AC servo devices, uninterruptible power sources (UPS), and switching power sources, to consumer applications, which include devices such as microwave ranges, electric rice cookers, and strobes. Development directed to next-generation IGBTs also is proceeding. An IGBT having a new chip structure with an even lower on-voltage has been developed so that devices using such IGBTs have reduced loss and enhanced efficiency.
IGBT structures may be mainly classified into types including a punch through (PT) type, a non-punch through (NPT) type, and a field stop (FS) type. Furthermore, almost all currently mass-produced IGBTs have an n-channel type vertical double-diffused structure except for those having a p-channel type structure used for audio power amplifiers. In the following, the term “IGBT” refers to as an n-type IGBT unless otherwise specified. Also, in the following descriptions and accompanying drawings, a layer or an area prefixed with a letter n or p means that a large number of electrons or holes are carried, respectively. Also, signs + and − attached to a letter n or p as superscripts mean that impurity concentrations are, respectively, higher and lower than a layer or an area without the sign.
A PT type IGBT has a structure in which an n+-layer (n-buffer layer) is provided between a p+-epitaxial substrate and an n−-layer (n-type active layer) to allow a depletion layer in the n-type active layer to reach the n-buffer layer. This is the basic structure for main stream IGBTs. However, for an IGBT of the 600 V breakdown series, although the n-type active layer needs a thickness only on the order of 70 μm, the total thickness including the p+-epitaxial substrate part may become as thick as on the order of 200 μm to 300 μm. This leads to development of the NPT type IGBT and the FS type IGBT. In each type, no epitaxial substrate is used. Instead, an FZ substrate is used that is formed by the FZ (Floating Zone) method to form therein a shallow p+-collector layer doped with a low dose so as to be thinned and provided at a reduced cost.
FIG. 12 is a view showing an example of a cross-sectional structure of an NPT type IGBT. NPT type IGBT 100 shown in FIG. 12 has a structure in which n−-type FZ (FZ-N) substrate 1 has gate electrode 5 of a material, such as polysilicon, formed on the top surface with gate oxide film 4 of a material, such as SiO2, provided between the substrate and the gate electrode. In this structure, top surface electrode 6, made of an aluminum silicon film, for example, is further formed on gate electrode 5 with interlayer insulator film 7 of a material, such as BPSG (Boro-Phospho Silicate Glass), provided between the top surface electrode 6 and the gate electrode 5. On the top surface side of FZ-N substrate 1, p+-base layer 2 and n+-emitter layer 3 in p+-base layer 2 are formed. On the bottom surface side of FZ-N substrate 1 is formed p+-collector layer 8 on which bottom surface electrode 9 is formed by laminating several kinds of metal films.
In NPT type IGBT 100 with such a structure, for the p+-collector layer 8, a shallow low-level injection p+-collector is used which is doped with a low dose. In NPT type IGBT 100, no p+-epitaxial substrate is used to make the total thickness thereof significantly less as compared with that of the above-described PT type IGBT.
In the NPT structure, hole injection rate can be controlled to enable high-speed switching without performing lifetime control of holes. The value of an on-voltage, which is dependent on the thickness and specific resistance of an n-type active layer, becomes a little higher. The use of the FZ substrate instead of the above-described p+-epitaxial substrate allows a chip with the NPT structure to be produced at a reduced cost.
FIG. 13 is a view showing an example of a cross-sectional structure of an FS type IGBT. In FIG. 13, the same constituents as those shown in FIG. 12 are denoted by the same reference numerals and signs with detailed explanations thereof omitted. For FS type IGBT 200 shown in FIG. 13, as for the above-described NPT type IGBT 100, FZ-N substrate 1 is used instead of the above-described p+-epitaxial substrate, with the total thickness thereof becoming on the order of 100 μm to 200 μm. As in the PT type IGBT, the n-type active layer is made to have a thickness on the order of 70 μm according to a breakdown voltage of 600 V and is made depleted. For this purpose, in FS type IGBT 200, on the bottom surface of FZ-N substrate 1, an n+-layer (n-buffer layer) 10 is formed, and p+-collector layer 8 and bottom surface electrode 9 are formed on the n-buffer layer 10. In FS type IGBT 200, as in the above-described NPT type IGBT 100, lifetime control is unnecessary.
In order to lower the on-voltage, a type of IGBT is used in which an IGBT with a trench structure, having a narrow and deep trench formed on the top surface of the IGBT together with a MOS gate formed on the side wall of the trench, is combined with an IGBT of an FS structure. Recently, total thickness reduction by design optimization also has been carried out.
Using the FS type IGBT 200 shown in the above-described FIG. 13 as an example, one example of a method of forming an IGBT will be explained with reference to FIG. 14 to FIG. 18. FIG. 14 is a cross-sectional view taken after a top surface side process has been completed. FIG. 15 is a cross-sectional view showing a substrate grinding process. FIG. 16 is a cross-sectional view showing a bottom surface side ion-implantation process. FIG. 17 is a cross-sectional view showing a bottom surface annealing process. FIG. 18 is a cross-sectional view showing a bottom surface electrode film-forming process. In FIG. 14 through FIG. 18, the same constituents as those shown in FIG. 12 and FIG. 13 are denoted by the same reference numerals and signs with detailed explanations thereof omitted.
The processes of forming FS type IGBT 200 may be roughly classified into a top surface side process and a bottom surface side process. First, an explanation will be given about the top surface side process with reference to FIG. 14. In the top surface side process, SiO2 and polysilicon are first deposited in that order on the top surface side of FZ-N substrate 1. The deposited SiO2 and polysilicon are then processed to form a window that penetrates gate oxide film 4 and gate electrode 5, respectively. Following this, BPSG is deposited on the surface thereof. The deposited BPSG is then processed to form a window into interlayer insulator film 7. This provides an insulated gate structure formed on the top surface side of FZ-N substrate 1.
Next, p+-base layer 2 is formed on the top surface side of the FZ-N substrate 1 and n+-emitter layer 3 is also formed in p+-base layer 2. Furthermore, an aluminum silicon film is deposited so that it is in contact with n+-emitter layer 3. This layer is top surface electrode 6 that is to become the emitter electrode. The aluminum silicon film is thereafter heat-treated at a low temperature on the order of 400° C. to 500° C. to realize an interconnection with stable compatibility and low resistance.
Although its illustration was omitted in FIG. 13 and FIG. 14, an insulator protective film is formed on the top surface electrode 6 using a material, such as a polyimide, so as to cover the surface thereof. Next, an explanation will be given about the bottom surface side process with reference to FIG. 15 to FIG. 18. In the bottom surface side process, as shown in FIG. 15, FZ-N substrate 1 is first thinned from the bottom surface to a desired thickness by carrying out back grinding or etching to produce a thinned wafer.
Next, as shown in FIG. 16, phosphorous ions (P+) and boron ions (B+) are implanted in this order onto the bottom surface side of FZ-N substrate 1 to form n+-layer 10a and p+-layer 8a, which are thereafter heat-treated (annealed) at a low temperature of 350° C. to 500° C. in an electric furnace. This activates phosphorous-implanted n+-layer 10a and boron-implanted p+-layer 8a to form n+-buffer layer 10 and p+-collector layer 8, respectively, on the bottom surface side of FZ-N substrate 1 as shown in FIG. 17. There may be a case where BF2 is implanted after the implantation of boron so as to form a top surface contact layer (p-layer) that comes in ohmic contact with the bottom surface electrode on the uppermost surface layer of p+-collector layer 8.
Thereafter, as shown in FIG. 18, bottom surface electrode 9 is formed on the surface of p+-collector layer 8. It is made up of a combination of metal layers, such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer. Finally, the wafer is subjected to dicing into chip-like pieces. Then, onto each of the chip-like pieces, aluminum wire electrodes are fixed by means of an ultrasonic wire bonder onto the surface of top surface electrode 6. Bottom surface electrode 9 is connected to a specified fixing piece with a solder layer provided there between.
In recent years, a matrix converter that carries out direct AC to AC conversion without intervention of a direct current has been spotlighted. Unlike previous inverters, the matrix converter requires no capacitor and thereby has an advantage that supply harmonics are reduced. However, an alternating current input requires a semiconductor switch to have a high reverse breakdown voltage. Thus, use of an IGBT of this previous type needed a reverse-blocking diode connected in series thereto.
FIG. 19 is a view showing an example of a cross-sectional structure of a reverse-blocking IGBT. In FIG. 19, the same constituents as those shown in FIG. 12 are denoted by the same reference numerals and signs with detailed explanation thereof omitted. As is shown in FIG. 19, reverse-blocking IGBT 300 is an IGBT which has a basic performance following that of the previous type IGBT with p+-isolation layer 11 further formed so as to provide a high reverse breakdown voltage. For a reverse-blocking IGBT 300 having such a structure, no diode connected in series is necessary to allow conduction loss to be reduced by half. This largely contributes to enhancement of the conversion efficiency of the matrix converter. The technology of forming a deep junction with a depth of 100 μm or more and the technology of producing a very thin wafer with a thickness of 100 μm or less are combined to enable manufacture of a high performance reverse-blocking IGBT.
In manufacturing such an IGBT, however, there are many technical aspects of the manufacturing process that must be addressed in order to realize a thin IGBT with a thickness on the order of 70 μm. These include elimination of warping of the wafer that is caused by necessary processing, such as bottom surface back grinding, ion-implantation to the bottom surface, and bottom surface heat-treatment.
One of the technical aspects of the manufacturing processes is the technique of activating a p-type doped layer (p-layer) or an n-type doped layer (n-layer), which is necessary in order to form various kinds of semiconductor elements including the IGBTs shown here as examples. Various methods have been tried previously for this activation. Besides the method of using an electric furnace as described above, activation of a doped layer has been carried out by annealing using a laser. In this technique, for example, a wafer is secured on a supporting substrate by an adhesive sheet to prevent cracking of the wafer and the wafer is irradiated with a laser beam to activate the p-layer and the n-layer. Activation may be carried out using the second harmonic of a YAG (Yttrium Aluminum Garnet) laser (YAG2ω laser) or the third harmonic thereof (YAG3ω laser).
In activating the p-layer and the n-layer in the case of previous electric furnace annealing, however, the p-layer cannot be made highly activated. Furthermore, in the method of using an adhesive sheet for preventing cracking of the wafer, the permissible temperature of the adhesive sheet is usually 200° C. or less which makes the use of the sheet impossible when the electric furnace annealing needs to be carried out at 300° C. or more.
Moreover, when the p-layer and the n-layer are to be activated by laser annealing instead of electric furnace annealing, irradiation with a short single pulsed laser beam with a full-width at half maximum smaller than 100 ns, such as a pulsed beam of an excimer laser, can activate only to a shallow region from the surface. For example, in pn-successive layers on the bottom surface side of an FS type IGBT where the p-layer and the n-layer are successively provided from the bottom surface in that order, sufficient activation up to the n-layer is impossible. When irradiation is carried out with a beam of an all-solid-state laser, such as the YAG2ω laser and the YAG3ω laser, used in the form of a signal pulse, the irradiation being carried out with a beam spot with a diameter on the order of 0.9 mm, for example, necessitates a long irradiation time. Thus, the processing time for one wafer can be several hours. For example, annealing of a five-inch wafer takes on the order of two hours. Moreover, when one irradiation area is irradiated with a laser beam in which irradiation energy density has been increased, traces of work damage by the laser irradiation sometime remain on the surface of the wafer.
As one measure to address the problems discussed above, the inventor proposed a method of activating a doped layer into which an impurity has been introduced by continuously irradiating plural pulses onto the doped layer from one irradiation area to another with the use of plural laser irradiation devices that irradiate pulsed laser beams, for example, in JP-A-2005-223301 (paragraph numbers 0026 and 0027) and U.S. Pat. No. 7,135,387. Also, a method of activating impurity ions implanted into a deep part of a wafer with the use of a semiconductor laser has been proposed, for example, in JP-A-2006-351659 (paragraph number 0012). Further, use of selenium or sulfur as a dopant when forming an n-doped layer has been proposed, for example, in JP-A-2002-520885 (paragraph numbers 0014 and 0032) and U.S. Pat. No. 6,441,408. Selenium and sulfur have an extremely high diffusion coefficient for silicon as compared with a dopant in the related art.
However, because the diffusion coefficient of a dopant in the related art, such as P (phosphorous) and As (arsenic), is not so large, they hardly diffuse by laser irradiation for an irradiation time on the order of several ns. In addition, the depth of a doped layer that can be activated by laser irradiation is 1.5 μm or less. Hence, for example, in order to activate the p+-collector layer and the n-buffer layer in FS type IGBT by laser irradiation, the p+-collector layer and the n-buffer layer have to be formed shallow. In the case where these layers are formed shallow, flaws or adhesion of dirt frequently occurs on the bottom surface of the substrate during the process steps. Leakage current increases when the n-buffer layer is not formed properly in part because of such flaws or dirt. This raises the problem that device failure readily occurs.
In addition, in the case where a dopant having a large diffusion coefficient is used, the dopant penetrates through the substrate and comes off of the substrate when heat treatment for diffusion and activation is carried out for a long time. This raises another problem in that a desired characteristic cannot be achieved in a stable manner. Further, when a laser beam is irradiated onto a thin wafer using a top surface side process and back grinding from the bottom surface side of the wafer, the surface on the opposite side to the laser beam irradiation surface, that is, the surface on which the gate structure or the like has been formed in the top surface side processing, becomes hot. For example, when the thickness of the wafer is 70 μm, the temperature on the top surface side of the wafer may possibly become as high as about 500° C., which causes the top surface electrode and the insulator protective film on top thereof to melt. This raises still another problem of a broken device.
In order to solve the problems in the related art discussed above, the invention has as an object to provide a method of manufacturing a semiconductor element that can prevent the occurrence of a device failure. Also, the invention has as another object to provide a method of manufacturing a semiconductor element that can manufacture a semiconductor element having satisfactory device characteristics. Further, the invention has as still another object to provide a method of manufacturing a semiconductor element that can prevent breaking of a device by heat induced during laser irradiation.